1. Field of the Invention
This application relates to receivers for high speed data and more particularly to slice levels used in such receivers to set a threshold at which an incoming signal is determined to be a one or zero.
2. Description of the Related Art
FIG. 1 shows the block diagram of a typical high-speed optical receiver system 100. The received optical energy 101 is converted to a current using a photodiode, 103. The photodiode signal current I0 is converted to a voltage using the transimpedance amplifier (TIA) 105. The signal at the output of TIA 105 is small for low optical energy signals, and can contain significant corruption due to, e.g., noise and limited rise and fall times. The output of TIA 105 is followed by additional gain, usually implemented with a limiting amplifier or an automatic gain control (AGC) amplifier 107. The clock and data recovery circuit 109 recovers both the data and the clock typically embedded in the input data stream received by the photodiode D1 and provides differential clock and data signals 111 and 113, respectively.
The function of the limiting amplifier is to produce a consistent waveform from the TIA output, which can be used by a clock and data recovery circuit (CDR) 109, irrespective of the incoming optical energy. The clock and data recovery circuit 109 recovers both the data and the clock typically embedded in the input data stream received by the photodiode 103 and provides differential clock and data signals 111 and 113.
The TIA output voltage is shown in FIG. 2A. At low levels of optical energy (corresponding to a zero level bit for example), the noise current is low. At higher levels of optical energy (corresponding to a one-level bit), the noise current may be higher. This asymmetry, as shown in FIG. 2A, may require an introduction of an intentional offset, to create a more reliable output. FIG. 2B illustrates this asymmetry by showing that the distribution of 0's is much tighter than the distribution of 1's. The intentional offset utilized to account for this asymmetry is referred to as a slice level.
A slice level can be thought of as the threshold voltage at which an incoming signal is determined to be either a “1” bit or a “0” bit. An adjustable slice level can compensate for the asymmetric noise characteristic present in the photodiode and the TIA output or for some nonlinearly in the TIA and photodiode.
As shown in FIG. 2A, a slice level of zero gives a smaller amount of margin for the positive swing compared to the negative swing. If the threshold is set to roughly −2 mV in the case shown, the margin is more symmetric and better results are to be expected. Thus, introducing a small offset serves to optimize noise margin and signal strength. Amplifier stage 107 utilizes an adjustable slicing level to compensate for the asymmetric noise characteristic present in the photodiode output.
Referring now to FIG. 3, an internal terminating resistor 301 is typically used in high speed systems to terminate a high speed data path. Assuming the resistance of the signal line 303 is 50 ohms and a 20 mV signal was supplied to the signal line 303, if resistor 301 were an ideal 50 ohms, the voltage at node 305 would be 10 mV. However, the on chip resistor 301 is not ideal and in fact varies by, e.g., 15%, due to such factors as process and temperature variations. Thus, although a slice voltage level is specified to account for noise margin and signal strength, the slice voltage does not account for the variation in signal level due to the non-ideal nature of the terminating resistor 301. That error is approximately ΔR/2, where ΔR represents the difference from the nominal value of R.
It would be desirable to adjust the slice voltage to account for the variation in resistance of the terminating resistance.